In the field of semiconductor production, with achievement of high performance of ultra LSI devices, a miniaturization technology as an extension of the conventional technology finds restriction in allowing high integration and speed-up to be compatible with each other. Accordingly, techniques for allowing vertical high integration while miniaturization of semiconductor elements is being promoted, namely, techniques for developing multilayered wiring have been developed.
In the process for producing a device comprising multilayered wiring, one of the most important techniques is a CMP technique. The CMP technique is a technique in which a thin film is formed on a substrate by, for example, chemical vapor deposition (CVD), and then its surface is flattened. For example, a treatment based on CMP is indispensable for the purpose of securing the depth of focus in lithography. When the substrate surface has irregularities, there occur, for example, such troubles that the focusing in an exposure step is precluded, or fine wiring structure cannot be sufficiently formed. The CMP technique is applied, in a production process of a device, to a step of forming an element isolation region by polishing a plasma oxide material (for example, BPSQ HDP-SiO2, or p-TEOS), a step of forming an interlayer insulating material, or a step of flattening a plug (for example, Al·Cu plug) after a silicon oxide-containing member (for example, a silicon oxide film) is embedded in a metal wiring.
CMP is usually performed using an apparatus capable of supplying a polishing liquid to a polishing pad. The substrate surface is polished by pressing the substrate against the polishing pad and by moving at least one of the substrate and the polishing pad while a polishing liquid is being supplied between the substrate surface and the polishing pad. In the CMP technique, a high-performance polishing liquid is one of the essential technologies, and various polishing liquids have hitherto been developed (for example, see following Patent Literature 1).